1. Field of the Invention
The present invention relates to a technique for manufacturing a semiconductor device. More particularly, the present invention relates to a plasma processing apparatus and a plasma processing method suitable for manufacturing a semiconductor device.
2. Description of the Related Art
A plasma processing method for semiconductor manufacturing includes plasma etching. In the plasma etching, a sample substrate (wafer) is mounted on a sample stage in a processing chamber, and exposed to plasma. At this time, various processing conditions, such as gas species introduced into the processing chamber and radio frequency power applied to the wafer, are adjusted to selectively remove a specific layered film on the wafer and form a fine circuit pattern on the wafer.
For processing different films, any of processing conditions needs to be changed according to a film to be processed. Since the plasma processing is desirably performed in a stable plasma state, the processing conditions are normally changed during interruption of plasma discharge. Thus, plasma discharge and interruption of the discharge is generally repeated, in the plasma etching.
In a plasma etching as described above, for fulfilling a request for prevention of displacement of the wafer during processing, wafer temperature control, or the like, the wafer is normally secured on a sample stage using an electrostatic chuck electrode or the like. When the wafer is secured on the sample stage using the electrostatic chuck electrode, potential may be generated on a surface of the wafer according to a potential of the electrostatic chuck electrode. The potential generated on the surface of the wafer may cause discharge in a vacuum to bring about breakage of a device or wiring on the wafer. Thus, the potential over the surface of the wafer is desirably suppressed. A method of suppressing the potential over the surface of the wafer during chucking the wafer onto the sample stage using the electrostatic chuck electrode includes the following.
WO 2009/013803 says that, in a bipolar chuck electrode, when electrode portions have asymmetric areas or when distances between the electrode portions and a wafer are different although pattern rules including the area and the width are identical between both electrode portions, application of a voltage of the same absolute value to both electrode portions tends to deviates a potential over a wafer chuck surface to a potential of an electrode having a large area or a potential of a first electrode layer near a surface layer. For this reason, WO 2009/013803 discloses a technique in which a set of voltages having different polarities is applied to a first electrode portion and a second electrode portion to reduce the potential over the wafer chuck surface on which the wafer is electrostatically chucked, for cancellation of imbalance in surface potential caused by the asymmetric areas of both electrode portions.